View MT48H4M16LFB4-10IT_7902751.PDF datasheet online --- IC-ON-LINE

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products and specifications discussed herein are subject to change by micron without notice. pdf: 09005aef80a63953, source: 09005aef808a7edc y25l_64mb_1.fm - rev. e 11/04 en 1 ?2004 micron technology, inc. all rights reserved. 64mb: x16 mobile sdram synchronous dram mt48h4m16lf - 1 meg x 16 x 4 banks features ? temperature compensated self refresh (tcsr) fully synchronous; all signals registered on positive edge of system clock internal pipelined operation; column address can be changed every clock cycle internal banks for hiding row access/precharge programmable burst length s: 1, 2, 4, 8, or full page auto precharge, includes concurrent auto precharge, and auto refresh modes self refresh mode; standard and low power 64ms, 4,096-cycle refresh lvttl-compatible inputs and outputs low voltage power supply partial array self refresh power-saving mode deep power-down mode programmable output drive strength operating temperature ranges: extended (-25c to +85c) industrial (-40c to +85c) fbga part number system due to space limitations, fbga-packaged compo- nents have an abbreviated part marking that is differ- ent from the part number. for a quick conversion of an fbga code, see the fbga part marking decoder on the micron web site, www.micron.com/decoder . figure 1: 54-ball fbga pin assignment (top view) options marking v dd /v dd q 1.8v/1.8v h configurations 4 meg x 16 (1 meg x 16 x 4 banks) 4m16 package/ball out 54-ball fbga, 8mm x 8mm (standard) f4 54-ball fbga, 8mm x 8mm (lead-free) b4 timing (cycle time) 8ns @ cl = 3 (125 mhz) -8 9.6ns @ cl = 3 (104 mhz) -10 operating temperature extended (-25 c to +85 c) none industrial (-40 c to +85 c) it table 1: address table 4 meg x 16 configuration 1 meg x 16 x 4 banks refresh count 4k row addressing 4k (a0?a11) bank addressing 4 (ba0, ba1) column addressing 256 (a0?a7) table 2: key timing parameters cl = cas (read) latency speed grade clock frequency access time setup time hold time cl = 2 cl = 3 -8 125 mhz 6ns 2.5ns 1ns -10 104 mhz ? 7ns 2.5ns 1ns -8 104 mhz 8ns ? 2.5ns 1ns -10 83 mhz 8ns - 2.5ns 1ns a b c d e f g h j 1 2 3 4 5 6 7 8 top view (ball down) v ss dq14 dq12 dq10 dq8 udqm nc/a12 a8 v ss dq15 dq13 dq11 dq9 nc clk a11 a7 a5 v ss q v dd q v ss q v dd q v ss cke a9 a6 a4 v dd q v ss q v dd q v ss q v dd cas# ba0 a0 a3 dq0 dq2 dq4 dq6 ldqm ras# ba1 a1 a2 v dd dq1 dq3 dq5 dq7 we# cs# a10 v dd 9
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mtoc.fm - rev. e 11/04 en 2 ?2003 micron technology, inc. all rights reserved. table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 fbga part number system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 list of tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 cas latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 write burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 temperature compensated self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 partial array self refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 driver strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 command inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 no operation (nop). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 load mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 deep power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 bank/row activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 deep power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 clock suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 burst read/single write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 concurrent auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 read with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 write with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 data sheet designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mlof.fm - rev. e 11/04 en 3 ?2003 micron technology, inc. all rights reserved. list of figures figure 1: 54-ball fbga pin assignment (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: part numbering diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 3: functional block diagram 4 meg x 16 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 4: mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 5: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 6: extended mode register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 7: activating a specific row in a specific bank register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 8: meeting trcd (min) when 2 < trcd (min)/tck< 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 9: read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 10: consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 11: random read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 12: read to write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 13: read to write with extra clock cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 14: read to precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 15: terminating a read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 16: write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 17: write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 18: write to write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 19: random write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 20: write to read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 21: write to precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 22: power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 23: terminating a write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 24: precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 25: clock suspend during write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 26: clock suspend during read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 27: read with auto precharge interrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 28: read with auto precharge interrupted by a write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 29: write with auto precharge interrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 30: write with auto precharge interrupted by a write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 31: initialize and load mode register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 32: power-down mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 33: clock suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 34: auto refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 35: self refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 36: read ? without auto precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 37: read ? with auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 38: single read ? without auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 39: single read ? with auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 40: alternating bank read accesses 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 41: read ? full-page burst 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 42: read ? dqm operation 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 43: write ? without auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 44: write ? with auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 45: single write ? without auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 46: single write ? with auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 47: alternating bank write accesses 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 48: write ? full-page burst 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 49: write ? dqm operation 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 50: 54-ball fbga (8mm x 8mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mlot.fm - rev. e 11/04 en 4 ?2003 micron technology, inc. all rights reserved. list of tables table 1: address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: key timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 3: ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 4: burst definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 5: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 6: truth table 1 ? commands and dqm operation 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 7: truth table 2 ? cke . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 8: truth table 3 ? current state bank n , command to bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 9: truth table 4 ? current state bank n , command to bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 10: dc electrical characteristics and operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 11: ac electrical characteristics and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 12: electrical characteristics and recommended ac operating conditions . . . . . . . . . . . . . . . . . . . . . . .31 table 13: ac functional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 14: i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 15: i dd 7 - self refresh current options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 16: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 5 ?2003 micron technology, inc. all rights reserved. figure 2: part numbering diagram general description the micron ? 64mb sdram is a high-speed cmos, dynamic random-access memory containing 67,108,864-bits. it is internally configured as a quad- bank dram with a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the x16?s 16,777,216-bit banks is orga- nized as 4,096 rows by 256 columns by 16 bits. read and write accesses to the sdram are burst ori- ented; accesses start at a selected location and con- tinue for a programmed number of locations in a programmed sequence. accesses begin with the regis- tration of an active command, which is then fol- lowed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0?a11 select the row). the address bits registered coincident with the read or write command are used to select the starting col- umn location for the burst access. the sdram provides for programmable read or write burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. the 64mb sdram uses an internal pipelined archi- tecture to achieve high-speed operation. this architec- ture is compatible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high- speed, fully random access. precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless high-speed, random-access operation. the 64mb sdram is designed to operate in 1.8v, low-power memory systems. an auto refresh mode is provided, along with a power-saving, deep power- down mode. all inputs and outputs are lvttl-com- patible. sdrams offer substantial advances in dram oper- ating performance, including the ability to synchro- nously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. ? configuration mt48 v dd / v dd q package speed v dd /v dd q 1.8/1.8v h configuration 4 meg x16 4m16lf package f4 b4 speed grade 8ns 9.6ns -8 -10 example part number: mt48h4m16lf-8 it 54-ball vfbga (8mm x 8mm) 54-ball vfbga (8mm x 8mm) lead-free temp none it operating temp extended industrial
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 6 ?2003 micron technology, inc. all rights reserved. figure 3: functional block diagram 4 meg x 16 sdram 12 ras# cas# row- address mux clk cs# we# cke control logic column- address counter/ latch mode register 8 command decode a0-a11, ba0, ba1 dqml, dqmh 12 address register 14 256 (x16) 4096 i/o gating dqm mask logic read data latch write drivers column decoder bank0 memory array (4,096 x 256 x 16) bank0 row- address latch & decoder 4096 sense amplifiers bank control logic dq0- dq15 16 16 data input register data output register 16 12 bank1 bank2 bank3 12 8 2 2 2 2 refresh counter ba1 ba0 bank 000 011 102 113
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 7 ?2003 micron technology, inc. all rights reserved. table 3: ball descriptions 54-ball fbga symbol type description f2 clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also increments the internal burst counter and controls the output registers. f3 cke input clock enable: cke activates (high) and deactivates (low) the clk signal. deactivating the clock provides precharge power-down and self refresh operation (all banks idle), active power-down (row active in any bank), deep power down (all banks idle), or clock suspend operation (burst/access in progress). cke is synchronous except after the device enters power-down and self refresh modes, where cke becomes asynchronous until after exiting the same mode. the input buffers, including clk, are disabled during power-down and self refresh modes, providing low standby power. cke may be tied high. g9 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is considered part of the command code. f7, f8, f9 cas#, ras#, we# input command inputs: cas#, ras#, and we# (along with cs#) define the command being entered. e8, f1 ldqm, udqm input input/output mask: dqm is sampled high and is an input mask signal for write accesses and an output enable signal for read accesses. input data is masked during a write cycle. the output buffers are placed in a high-z state (two-clock latency) when duri ng a read cycle. ldqm corresponds to dq0?dq7, udqm corresponds to dq8?dq15. ldqm and udqm are considered same state when referenced as dqm. g7, g8 ba0, ba1 input bank address input(s): ba0 and ba1 define to which bank the active, read, write or precharge command is being applied. these pins also select between the mode register and the extended mode register. h7, h8, j8, j7, j3, j2, h3, h2, h1, g3, h9, g2 a0?a11 input address inputs: a0?a11 are sampled during the active command (row- address a0?a11) and read/write command (column-address a0?a7; with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine if all banks are to be precharged (a10 high) or bank selected by ba0, ba1. the address inputs also provide the op-code during a load mode register command. a8, b9, b8, c9, c8, d9, d8, e9, e1, d2, d1, c2, c1, b2, b1, a2 dq0?dq15 i/o data input/output: data bus. e2, g1 nc ? these could be left unconnected, but it is recommended they be connected to v ss . g1 is a no connect for this part but may be used as a12 in future designs. a7, b3, c7, d3 v dd q supply dq power: provide isolated power to dqs for improved noise immunity. a3, b7, c3, d7 v ss q supply dq ground: provide isolated ground to dqs for improved noise immunity. a9, e7, j9 v dd supply core power supply. a1, e3, j1 v ss supply ground.
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 8 ?2003 micron technology, inc. all rights reserved. functional description in general, the 64mb sdrams (1 meg x 16 x 4 banks) are quad-bank drams that operate at 1.8v and include a synchronous interface (all signals are regis- tered on the positive edge of the clock signal, clk). each of the x16?s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. read and write accesses to the sdram are burst ori- ented; accesses start at a selected location and con- tinue for a programmed number of locations in a programmed sequence. accesses begin with the regis- tration of an active command, which is then fol- lowed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0 and ba1 select the bank, a0-a11 select the row). the address bits (a0?a7) registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the sdram must be ini- tialized. the following sections provide detailed infor- mation covering device initialization, register definition, command descriptions and device opera- tion. initialization sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined opera- tion. power should be applied to v dd and v dd q simul- taneously. once the power is applied to v dd and v dd q and the clock is stable (stable clock is defined as a sig- nal cycling within timing constraints specified for the clock pin), the sdram requires a 100s delay prior to issuing any command other than a command inhibit or nop. starting at some point during this 100s period and continuing at least through the end of this period, command inhibit or nop commands should be applied. once the 100s delay has been satisfied with at least one command inhibit or nop command having been applied, a precharge command should be applied. all banks must then be precharged, thereby placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. after the auto refresh cycles are com- plete, the sdram is ready for mode register program- ming. because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. mode register definition in order to achieve low power consumption, there are two mode registers in the mobile component, mode register and extended mode register. the mode register is illustrated in figure 4, mode register defini- tion, on page 9 (the extended mode register is illus- trated in figure 6, extended mode register table, on page 11). the mode register defines the specific mode of operation of the sdram, including burst length, burst type, cas latency, operating mode and write burst mode. the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power. mode register bits m0?m2 specify the burst length, m3 specifies the type of burst (sequential or inter- leaved), m4?m6 specify the cas latency, m7 and m8 specify the operating mode, m9 specifies the write burst mode, and m10, and m11 should be set to zero. m12 and m13 should be set to zero to prevent extended mode register. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. vio- lating either of these requirements will result in unspecified operation. burst length read and write accesses to the sdram are burst ori- ented, with the burst length being programmable, as shown in figure 4, mode register definition, on page 9. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. the full-page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a0?a7 when the burst length is set to two; by a2?a7 when the burst length is set to four; and by a3?a7 when the burst length is set to eight.
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 9 ?2003 micron technology, inc. all rights reserved. note: 1. for full-page accesses: y = 256. 2. for a burst length of two, a1?a7 select the block-of- two burst; a0 selects the starting column within the block. 3. for a burst length of four, a2?a7 select the block-of- four burst; a0?a1 select th e starting column within the block. 4. for a burst length of eight, a3?a7 select the block-of- eight burst; a0?a2 select the starting column within the block. 5. for a full-page burst, the full row is selected and a0?a7 select the starting column. 6. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. for a burst length of one, a0?a7 select the unique col- umn to be accessed, and mode register bit m3 is ignored. figure 4: mode register definition the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is deter- mined by the burst length, the burst type and the start- ing column address, as shown in table 4. table 4: burst definition burst length order of accesses within a burst starting column address ty pe = sequential ty pe = interleaved 2 a0 00-1 0-1 11-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page (y) n = a0?a7 (location 0-y) cn, cn+1, cn+2, cn+3, cn+4..., ?cn-1, cn? not supported 10 m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleaved cas latency reserved 1 2 3 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 op mode a10 reserved* wb 0 1 write burst mode programmed burst length single location access m9 *should program m10 = ?0, 0? to ensure compatibility with future devices. ba0 ba1 m9 m7 m6 m5 m4 m3 m8 m2 m1 m0 m10 11 a11 m11 m12 m13 reserved** 13 12 ** ba1, ba0 = ?0, 0? to prevent extended mode register.
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 10 ?2003 micron technology, inc. all rights reserved. cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data. the latency can be set to one, two, or three clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by clock edge n + m . the dqs will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all rele- vant access times are met, if a read command is regis- tered at t0 and the latency is programmed to two clocks, the dqs will start driving after t1 and the data will be valid by t2, as shown in figure 5, cas latency. table 5, indicates the operating frequencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. figure 5: cas latency operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m0- m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single-location (non- burst) accesses. extended mode register the extended mode register controls the functions beyond those controlled by the mode register. these additional functions are special features of the mobile device. they include temperature compensated self refresh (tcsr) control, partial array self refresh (pasr), and output drive strength. not programming the extended mode register upon initialization, will result in default settings for the low power features. the extended mode will default to the +85 c setting for tcsr, full drive strength, and full array refresh. the extended mode register is programmed via the mode register set command (ba1 = 1, ba0 = 0) and retains the stored information until it is pro- grammed again or the device loses power. the extended mode register must be programmed with e6 through e11 set to ?0.? it must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiat- ing any subsequent operation. violating either of these requirements results in unspecified operation. once the values are entered the extended mode reg- ister settings will be retained even after exiting deep power-down. clk dq t2 t1 t3 t0 cas latency = 3 lz d out t oh t c om mand nop read t ac nop t 4 nop don?t car e undefined clk dq t2 t1 t3 t0 cas latency = 2 lz d out t oh t c om mand nop read t ac nop table 5: cas latency speed allowable operating frequency (mhz) cas latency = 2 cas latency = 3 -8 104 125 -10 83.3 104
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 11 ?2003 micron technology, inc. all rights reserved. temperature compensated self refresh temperature compensated self refresh (tcsr) allows the controller to program the refresh interval during self refresh mode, according to the case tem- perature of the mobile device. this allows great power savings during self refresh during most operating temperature ranges. only during extreme tempera- tures would the controller have to select the maximum tcsr level. this would guarantee data during self refresh. every cell in the sdram requires refreshing due to the capacitor losing its charge over time. the refresh rate is dependent on temperature. at higher tempera- tures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often. historically, during self refresh, the refresh rate has been set to accommodate the worst case, or high- est temperature range expected. thus, during ambient temperatures, the power con- sumed during refresh was unnecessarily high, because the refresh rate was set to accommodate the higher temperatures. adjusting the refresh rate by setting e4 and e3 allows the sdram to accommodate more spe- cific temperature regions during self refresh. there are four temperature settings, which will vary the self refresh current according to the selected temperature. this selectable refresh rate will save power when the sdram is operating at normal tem- peratures. partial array self refresh for further power savings during self refresh, the partial array self refresh (pasr) feature allows the controller to select the amount of memory that will be refreshed during self refresh. the refresh options are all banks (banks 0, 1, 2, and 3); two banks (banks 0 and 1); and one bank (bank 0). also included in the refresh options are the 1/2 bank and 1/4 bank partial array self refresh (bank 0). write and read com- mands occur to any bank selected during standard operation, but only the selected banks in pasr will be refreshed during self refresh. it?s important to note that data in unused banks, or portions of banks, will be lost when pasr is used. data will be lost in banks 1, 2, and 3 when the one bank option is used. driver strength bits e5 and e6 of the extended mode register can be used to select the driver strength of the dq outputs. this value should be set according to the application?s requirements. full drive strength was carried over from standard sdram and is suitable to drive higher load systems. full drive strength is not recommended for loads under 30pf. half drive strength is intended for multi-drop systems with various loads. this drive option is not recommended for loads under 15pf. quarter drive strength is intended for lighter loads or point-to-point systems. figure 6: extende d mode register tabl e note: 1. e13 and e12 (ba1 and ba0) must be ?1, 0? to select the extended mode register (vs. the base mode register). 2. rfu: reserved for future use 3. default emr values are full array for pasr, full drive strength, and 85 for tcsr. 4. e11 = 0 5. e10, e11 = 0 maximum case temp e4 e3 a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a11 10 11 12 pasr tcsr 0 13 1 all must be set to "0" ba0 e9 e7 e6 e5 e4 e3 e8 e2 e1 e0 e10 e11 e12 ba1 e13 85?c 3 11 70?c 00 45?c 15?c 01 10 self refresh coverage four banks 3 two banks (bank 0,1) one bank (bank 0) rfu rfu 1/2 bank (bank 0) 4 1/4 bank (bank 0) 5 rfu e2 e1 e0 00 0 0 0 0 0 0 00 1 1 1 11 1 1 1 0 0 1 1 1 1 ds e5 e6 driver strength 0 0 0 0 1 1 11 full strength 3 quarter strength reserved half strength
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 12 ?2003 micron technology, inc. all rights reserved. commands figure 6, truth table 1 ? commands and dqm operation 1 provides a quick reference of available commands. this is followed by a written description of each command. three additional truth tables appear following the operation section; these tables provide current state/next state information. note: 1. cke is high for all commands shown except self refresh and deep power down 2. a0-a11 define op-code written to mode register. 3. a0?a11 provide row address, and ba0, ba 1 determine which bank is made active. 4. a0?a7 provide column address; a10 high enables the auto precharge feature (non persistent), while a10 low disables the auto precharge feature; ba0, ba1 determine which bank is being read from or written to. 5. a10 low: ba0, ba1 determine the bank being precharged . a10 high: all banks precharged and ba0, ba1 are ?don?t care.? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. 8. activates or deactivates the dqs during writes (zero-clock delay) and reads (two-clock delay). dqml controls dq0-7, dqmh controls dq8-15. 9. this command is burst terminate when cke is high and deep power down when cke is low. 10. the purpose of the burst terminate co mmand is to stop a data burst, thus the command could coincide with data on the bus. however the dqs column reads a don?t care state to illu strate that the burst terminate command can occur when there is no data present. table 6: truth table 1 ? commands and dqm operation 1 name (function) cs# ras# cas# we# dqm addr dqs notes command inhibit (nop) hxxx x x x no operation (nop) lhhh x x x active (select bank and activate row) l l h h x bank/row x 3 read (select bank and column, and start read burst) lhlhl/hbank/colx 4 write (select bank and column, and start write burst) l h l l l/h bank/col valid 4 burst terminate or deep power down (enter deep power down mode) lhhl x x x 9, 10 precharge (deactivate row in bank or banks) llhl xbank, a10x 5 auto refresh or self refresh (enter self refresh mode) lllh x x x 6, 7 load mode register/load extended mode register l l l l x op-code x 2 write enable/output enable xxxx l x active8 write inhibit/output high-z xxxx h x high-z8
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 13 ?2003 micron technology, inc. all rights reserved. command inhibit the command inhibit function prevents new commands from being executed by the sdram, regardless of whether the clk signal is enabled. the sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to an sdram which is selected (cs# is low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode register the mode register is loaded via inputs a0?a11, ba0, ba1. see mode register heading in the register defini- tion section. the load mode register and load extended mode register commands can only be issued when all banks are idle, and a subsequent exe- cutable command cannot be issued until t mrd is met. the values of the mode register and extended mode register will be retained even when exiting deep power-down. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a11 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a pre- charge command must be issued before opening a dif- ferent row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a7 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. read data appears on the dq subject to the logic level on the dqm inputs two clocks earlier. if a given dqm signal was registered high, the corresponding dq will be high-z two clocks later; if the dqm signal was regis- tered low, the dq will provide valid data. write the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a7 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dq is written to the memory array subject to the dqm input logic level appearing coincident with the data. if a given dqm signal is reg- istered low, the corresponding data will be written to memory; if the dqm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. auto precharge auto precharge is a feature which performs the same individual-bank precharge function described above, without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write com- mand. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst, except in the full-page burst mode, where auto precharge does not apply. auto precharge is non per- sistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that the precharge is initi- ated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge time ( t rp) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, as described for each burst type in the operation section of this data sheet.
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 14 ?2003 micron technology, inc. all rights reserved. auto refresh auto refresh is used during normal operation of the sdram and is analogous to cas#-before-ras# (cbr) refresh in conventional drams. this command is non persistent, so it must be issued each time a refresh is required. all active banks must be pre- charged prior to issuing an auto refresh com- mand. the auto refresh command should not be issued until the minimum t rp has been met after the precharge command as shown in the operation sec- tion. the addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto refresh command. the 64mb sdram requires 4,096 auto refresh cycles every 64ms ( t ref). providing a distributed auto refresh command every 15.625s will meet the refresh requirement and ensure that each row is refreshed. alternatively, 4,096 auto refresh commands can be issued in a burst at the minimum cycle rate ( t rfc), once every 64ms. self refresh the self refresh command can be used to retain data in the sdram, even if the rest of the system is powered down, as long as power is not completely removed from the sdram. when in the self refresh mode, the sdram retains data without external clock- ing. the self refresh command is initiated like an auto refresh command except cke is disabled (low). once the self refresh command is regis- tered, all the inputs to the sdram become ?don?t care? with the exception of cke, which must remain low. once self refresh mode is engaged, the sdram pro- vides its own internal clocking, causing it to perform its own auto refresh cycles. the sdram must remain in self refresh mode for a minimum period equal to t ras and may remain in self refresh mode for an indef- inite period beyond that. the procedure for exiting self refresh requires a sequence of commands. first, clk must be stable (sta- ble clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to cke going back high. once cke is high, the sdram must have nop commands issued (a minimum of two clocks) for t xsr because time is required for the com- pletion of any internal refresh in progress. upon exiting the self refresh mode, auto refresh commands should be issued at once and then every 15.625s or less, as both self refresh and auto refresh utilize the row refresh counter. deep power-down the operating mode deep power-down achieves maximum power reduction by eliminating the power of the whole memory array of the device. array data will not be retained once the device enters deep power-down mode. this mode is entered by having all banks idle then cs# and we# held low with ras# and cas# held high at the rising edge of the clock, while cke is low. this mode is exited by asserting cke high.
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 15 ?2003 micron technology, inc. all rights reserved. operation bank/row activation before any read or write commands can be issued to a bank within the sdram, a row in that bank must be ?opened.? this is accomplished via the active command, which selects both the bank and the row to be activated (see figure 7, activating a spe- cific row in a specific bank register). after opening a row (issuing an active command), a read or write command may be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specification of 20ns with a 125 mhz clock (8ns period) results in 2.5 clocks, rounded to 3. this is reflected in figure 8, which covers any case where 2 < t rcd (min)/ t ck 3. (the same procedure is used to convert other specification limits from time units to clock cycles.) a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the mini- mum time interval between successive active com- mands to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access over- head. the minimum time interval between successive active commands to different banks is defined by t rrd. figure 7: activating a specific row in a specific bank register figure 8: meeting t rcd (min) when 2 < t rcd (min)/ t ck< 3 cs# we# cas# ras# cke clk a0?a10, a11 row address don?t care high ba0, ba1 bank address clk t2 t1 t3 t0 t command nop active read or write t4 nop rcd don?t care
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 16 ?2003 micron technology, inc. all rights reserved. reads read bursts are initiated with a read command, as shown in figure 8. the starting column and bank addresses are pro- vided with the read command, and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is pre- charged at the completion of the burst. for the generic read commands used in the following illustrations, auto precharge is disabled. during read bursts, the valid data-out element from the starting column address will be available fol- lowing the cas latency after the read command. each subsequent data-out element will be valid by the next positive clock edge. figure 5, cas latency, on page 10, shows general timing for each possible cas latency setting. upon completion of a burst, assuming no other commands have been initiated, the dq will go high-z. a full-page burst will continue until terminated. (at the end of the page, it will wrap to column 0 and continue.) data from any read burst may be truncated with a subsequent read command, and data from a fixed- length read burst may be immediately followed by data from a read command. in either case, a continu- ous flow of data can be maintained. the first data ele- ment from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. the new read command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 10, consecutive read bursts, on page 17 for cas latencies of two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. the 64mb sdram uses a pipelined architecture and therefore does not require the 2 n rule associated with a prefetch architec- ture. a read command can be initiated on any clock cycle following a previous read command. full-speed random read accesses can be performed to the same bank, as shown in figure 11, random read accesses, on page 17, or each subsequent read may be per- formed to a different bank. data from any read burst may be truncated with a subsequent write command, and data from a fixed- length read burst may be immediately followed by data from a write command (subject to bus turn- around limitations). the write burst may be initiated on the clock edge immediately following the last (or last desired) data element from the read burst, pro- vided that i/o contention can be avoided. in a given system design, there may be a possibility that the device driving the input data will go low-z before the sdram dq go high-z. in this case, at least a single- cycle delay should occur between the last read data and the write command. figure 9: read command cs# we# cas# ras# cke clk column address a10 ba0,1 don?t care high enable auto precharge disable auto precharge bank address a0-a7 a9, a11
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 17 ?2003 micron technology, inc. all rights reserved. figure 10: consecutive read bursts note: each read command may be to any bank. dqm is low. figure 11: random read accesses note: each read command may be to any bank. dqm is low. the dqm input is used to avoid i/o contention, as shown in figure 12, read to write, and figure 13, read to write with extra clock cycle, on page18. the dqm signal must be asserted (high) at least two clocks prior to the write command (dqm latency is two clocks for output buffers) to suppress data-out from the read. once the write command is regis- tered, the dq will go high-z (or remain high-z), regardless of the state of the dqm signal, provided the dqm was active on the clock just prior to the write command that truncated the read command. if not, the second write will be an invalid write. for exam- ple, if dqm was low during t4 in figure 14, read to precharge, on page 18, then the writes at t5 and t7 would be valid, while the write at t6 would be invalid. the dqm signal must be de-asserted prior to the write command (dqm latency is zero clocks for input buffers) to ensure that the written data is not masked. figure 13, read to write with extra clock cycle, shows the case where the clock frequency allows for bus contention to be avoided without adding a nop cycle, and figure 13 shows the case where the additional nop is needed. a fixed-length read burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto pre- charge was not activated), and a full-page burst may be truncated with a precharge command to the same bank. the precharge command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 14 for each possible cas latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. following the precharge command, a subse- quent command to the same bank cannot be issued until t rp is met. note that part of the row precharge time is hidden during the access of the last data ele- ment(s). in the case of a fixed-length burst being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. the disadvantage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed-length or full-page bursts. don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 1 cycle cas latency = 2 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read nop t7 x = 2 cycles cas latency = 3 transitioning data clk dq t2 t1 t4 t3 t6 t5 t0 command address read nop nop bank, col n don?t care d out n d out a d out x d out m read read read nop bank, col a bank, col x bank, col m clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop bank, col n d out a d out x d out m read read read nop bank, col a bank, col x bank, col m cas latency = 2 cas latency = 3 transitioning data
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 18 ?2003 micron technology, inc. all rights reserved. figure 12: read to write note: a cas latency of three is used for illustration. the read command may be to any bank, and the write command may be to any bank. if a burst of one is used, then dqm is not required. figure 13: read to write with extra clock cycle note: a cas latency of three is used for illustration. the read command may be to any bank, and the write command may be to any bank. figure 14: read to precharge note: dqm is low. figure 15: terminating a read burst note: dqm is low. don?t care read nop nop write nop clk t2 t1 t4 t3 t0 dqm dq d out n command d in b address bank, col n bank, col b ds t hz t t ck don?t care read nop nop nop nop dqm clk dq d out n t2 t1 t4 t3 t0 command address bank, col n write d in b bank, col b t5 ds t hz t don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 x = 1 cycle cas latency = 2 cas latency = 3 x = 2 cycles bank a , col n bank a , row bank ( a or all) bank a , col n bank a , row bank ( a or all) transitioning data clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop t7 don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop x = 1 cycle cas latency = 2 cas latency = 3 x = 2 cycles transitioning data
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 19 ?2003 micron technology, inc. all rights reserved. full-page read bursts can be truncated with the burst terminate command, and fixed-length read bursts may be truncated with a burst termi- nate command, provided that auto precharge was not activated. the burst terminate command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 15, terminating a read burst, for each possible cas latency; data element n + 3 is the last desired data element of a longer burst. writes write bursts are initiated with a write command, as shown in figure 16, write command. the starting column and bank addresses are pro- vided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is pre- charged at the completion of the burst. for the generic write commands used in the following illustrations, auto precharge is disabled. during write bursts, the first valid data-in element will be registered coincident with the write com- mand. subsequent data elements will be registered on each successive positive clock edge. upon completion of a fixed-length burst, assuming no other commands have been initiated, the dq will remain high-z and any additional input data will be ignored (see figure 18, write to write). a full-page burst will continue until terminated. (at the end of the page, it will wrap to column 0 and continue.) figure 16: write command data for any write burst may be truncated with a subsequent write command, and data for a fixed- length write burst may be immediately followed by data for a write command. the new write com- mand can be issued on any clock following the previ- ous write command, and the data provided coincident with the new command applies to the new command. an example is shown in figure 19, random write cycles. data n + 1 is either the last of a burst of two or the last desired of a longer burst. the 64mb sdram uses a pipelined architecture and therefore does not require the 2 n rule associated with a prefetch architecture. a write command can be initiated on any clock cycle following a previous write command. full-speed random write accesses within a page can be performed to the same bank, as shown in figure 19, or each subsequent write may be performed to a differ- ent bank. cs# we# cas# ras# cke clk column address high enable auto precharge disable auto precharge bank address a0-a8 a10 ba0, 1 a9, a11 valid address don?t care
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 20 ?2003 micron technology, inc. all rights reserved. figure 17: write burst note: burst length = 2. dqm is low. figure 18: write to write note: dqm is low. each write command may be to any bank. data for any write burst may be truncated with a subsequent read command, and data for a fixed- length write burst may be immediately followed by a read command. once the read command is regis- tered, the data inputs will be ignored, and writes will not be executed. an example is shown in figure 20, write to read. data n + 1 is either the last of a burst of two or the last desi red of a longer burst. data for a fixed-length write burst may be fol- lowed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not activated), and a full-page write burst may be truncated with a precharge command to the same bank. the precharge command should be issued t wr after the clock edge at which the last desired input data element is registered. the auto precharge mode requires a t wr of at least one clock plus time, regard- less of frequency. in addition, when truncating a write burst, the dqm signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the precharge command. an example is shown in figure 21, write to precharge. data n + 1 is either the last of a burst of two or the last desired of a longer burst. following the precharge command, a subse- quent command to the same bank cannot be issued until t rp is met. in the case of a fixed-length burst being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. the disadvantage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed-length or full-page bursts. fixed-length or full-page write bursts can be trun- cated with the burst terminate command. when truncating a write burst, the input data applied coin- cident with the burst terminate command will be ignored. the last data written (provided that dqm is low at that time) will be the input data applied one clock previous to the burst terminate command. this is shown in figure 23, terminating a write burst, where data n is the last desired data element of a longer burst. clk dq d in n t2 t1 t3 t0 command address nop nop write d in n + 1 nop bank, col n don?t care clk dq t2 t1 t0 command address nop write write bank, col n bank, col b d in n d in n + 1 d in b don?t care
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 21 ?2003 micron technology, inc. all rights reserved. figure 19: random write cycles note: each write command may be to any bank. dqm is low. figure 20: write to read note: the write command may be to any bank, and the read command may be to any bank. dqm is low. cas latency = 2 for illustration. figure 21: write to precharge note: dqm could remain low in this example if the write burst is a fixed length of two. precharge the precharge command (see figure 24, pre- charge command, on page 22) is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specified time ( t rp) after the pre- charge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. clk dq d in n t2 t1 t3 t0 command address write bank, col n d in a d in x d in m write write write bank, col a bank, col x bank, col m don?t care clk dq t2 t1 t3 t0 command address nop write bank, col n d in n d in n + 1 d out b read nop nop bank, col b nop d out b + 1 t4 t5 don?t care dqm clk dq t2 t1 t4 t3 t0 command address bank a , col n t5 nop write precharge nop nop d in n d in n + 1 active t rp bank ( a or all) t wr bank a , row dqm dq command address bank a , col n nop write precharge nop nop d in n d in n + 1 active t rp bank ( a or all) t wr bank a , row t6 nop nop t wr @ t ck 15ns t wr @ t ck < 15ns don?t care
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 22 ?2003 micron technology, inc. all rights reserved. power-down power-down occurs if cke is registered low coinci- dent with a nop or command inhibit when no accesses are in progress. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding cke, for maxi- mum power savings while in standby. the device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. the power-down state is exited by registering a nop or command inhibit and cke high at the desired clock edge (meeting t cks). see figure 22, power- down. figure 22: power-down figure 23: terminating a write burst note: dqms are low. figure 24: precharge command deep power-down deep power down mode is a maximum power sav- ings feature achieved by shutting off the power to the entire memory array of the device. data on the mem- ory array will not be retained once deep power down mode is executed. deep power down mode is entered by having all banks idle then cs# and we# held low with ras# and cas# high at the rising edge of the clock, while cke is low. cke must be held low during deep power-down. in order to exit deep power down mode, cke must be asserted high. after exiting, the following sequence is needed in order to enter a new command. maintain nop input conditions for a minimum of 100us. issue precharge commands for all banks. issue eight or more autorefresh commands. the values of the mode register and extended mode register will be retained upon exiting deep power-down. clock suspend the clock suspend mode occurs when a column access/burst is in progress and cke is registered low. in the clock suspend mode, the internal clock is deacti- vated, ?freezing? the synchronous logic. for each positive clock edge on which cke is sam- pled low, the next internal positive clock edge is sus- pended. any command or data present on the input t ras t rcd t rc all banks idle input buffers gated off exit power-down mode. ( ) ( ) ( ) ( ) ( ) ( ) t cks > t cks command nop active enter power-down mode. nop clk cke ( ) ( ) ( ) ( ) don?t care clk dq t2 t1 t0 command address bank, col n write burst terminate next command d in n (address) (data) transitioning data cs# we# cas# ras# cke clk a10 don?t care high all banks bank selected a0-a9, a11 ba0,1 bank address valid address
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 23 ?2003 micron technology, inc. all rights reserved. pins at the time of a suspended internal clock edge is ignored; any data present on the dq pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (see examples in figure 25, clock suspend during write burst, and figure 26, clock suspend during read burst.) clock suspend mode is exited by registering cke high; the internal clock and related operation will resume on the subsequent positive clock edge. burst read/single write the burst read/single write mode is entered by pro- gramming the write burst mode bit (m9) in the mode register to a logic 1. in this mode, all write com- mands result in the access of a single column location (burst of one), regardless of the programmed burst length. read commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (m9 = 0). figure 25: clock suspend during write burst note: for this example, burst length = 4 or greater, and dm is low. figure 26: clock suspend during read burst note: for this example, cas latency = 2, burst length = 4 or greater, and dqm is low. d in command address write bank, col n d in n nop nop clk t2 t1 t4 t3 t5 t0 cke internal clock nop d in n + 1 d in n + 2 don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 cke internal clock nop don?t care
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 24 ?2003 micron technology, inc. all rights reserved. concurrent auto precharge micron sdram devices support concurrent auto precharge, which allows an access command (read or write) to another bank while an access command with auto precharge enabled is executing. four cases where concurrent auto precharge occurs are defined below. read with auto precharge 1. interrupted by a read (with or without auto precharge): a read to bank m will interrupt a read on bank n , two or three clocks later, depending on cas latency. the precharge to bank n will begin when the read to bank m is registered (figure 27, read with auto precharge interrupted by a read). 2. interrupted by a write (with or without auto precharge): when a write to bank m registers, a read on bank n will be interrupted. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered (figure 28, read with auto precharge interrupted by a write). figure 27: read with auto precharge interrupted by a read note: dqm is low. figure 28: read with auto precharge interrupted by a write note: dqm is high at t2 to prevent d out - a +1 from contending with d in - d at t4. clk dq d out a t2 t1 t4 t3 t6 t5 t0 command read - ap bank n nop nop nop nop d out a + 1 d out d d out d + 1 nop t7 bank n cas latency = 3 (bank m ) bank m address idle nop bank n , col a bank m , col d read - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active read with burst of 4 precharge rp - bank n t rp - bank m cas latency = 3 (bank n ) don?t care clk dq d out a t2 t1 t4 t3 t6 t5 t0 command nop nop nop nop d in d + 1 d in d d in d + 2 d in d + 3 nop t7 bank n bank m address idle nop dqm bank n , col a bank m , col d write - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active write with burst of 4 write-back rp - bank n t wr - bank m cas latency = 3 (bank n ) read - ap bank n 1 don?t care
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 25 ?2003 micron technology, inc. all rights reserved. write with auto precharge 3. interrupted by a read (with or without auto precharge): when a read to bank m registers, it will interrupt a write on bank n , with the data-out appearing 2 or 3 clocks later, (depending on cas latency). the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m (figure 29, write with auto pre- charge interrupted by a read). 4. interrupted by a write (with or without auto precharge): when a write to bank m registers, it will interrupt a write on bank n . the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid data write to bank n will be data registered one clock prior to a write to bank m (figure 30, write with auto precharge interrupted by a write). figure 29: write with auto precharge interrupted by a read note: dqm is low. figure 30: write with auto precharge interrupted by a write note: dqm is low. clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in a + 1 d in a nop nop t7 bank n bank m address bank n , col a bank m , col d read - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active read with burst of 4 t t rp - bank m d out d d out d + 1 cas latency = 3 (bank m ) rp - bank n wr - bank n don?t care clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in d + 1 d in d d in a + 1 d in a + 2 d in a d in d + 2 d in d + 3 nop t7 bank n bank m address nop bank n , col a bank m , col d write - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active write with burst of 4 write-back wr - bank n t rp - bank n t wr - bank m don?t care
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 26 ?2003 micron technology, inc. all rights reserved. note: 1. cke n is the logic state of cke at clock edge n ; cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the sdram immediately prior to clock edge n . 3. command n is the command registered at clock edge n , and action n is a result of command n . 4. all states and sequences not shown are illegal or reserved. 5. exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that t cks is met). 6. exiting self refresh at clock edge n will put the device in the all banks idle state once t xsr is met. command inhibit or nop commands should be issued on any clock edges occurring during the t xsr period. a minimum of two nop com- mands must be provided during t xsr period. 7. after exiting clock suspend at clock edge n , the device will resume operation and recognize the next command at clock edge n + 1. 8. deep power-down is a power-saving feature of this mob ile sdram device. this command is burst terminate when cke is high and deep power down when cke is low. table 7: truth table 2 ? cke notes: 1-4: notes appear below table cke n-1 cke n current state command n action n notes ll power-down x maintain power-down self refresh x maintain self refresh clock suspend x maintain clock suspend deep power-down x maintain deep power-down 8 lh power-down command inhibit or nop exit power-down 5 deep power-down x exit deep power-down 8 self refresh command inhibit or nop exit self refresh 6 clock suspend x exit clock suspend 7 hl all banks idle command inhibit or nop power-down entry all banks idle burst terminate deep power-down entry 8 all banks idle auto refresh self refresh entry reading or writing valid clock suspend entry h h see truth table 3
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 27 ?2003 micron technology, inc. all rights reserved. note: 1. this table applies when cke n-1 was high and cke n is high (see truth table 2) and after t xsr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are th ose allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. the following states must not be interrupted by a command issued to the same bank. command inhibit or nop commands, or allow- able commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the oth er bank are determined by its current state and truth table 3, and according to truth table 4. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the row active state. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto precharge enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 5. the following states must not be interrupted by any executable command; command inhibit or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rc is met. once t rc is met, the sdram will be in the all banks idle state. accessing mode register: starts with registration of a load mode register command and ends when t mrd has been met. once t mrd is met, the sdram will be in the all banks idle state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks will be in the idle state. 6. all states and sequences not shown are illegal or reserved. 7. not bank-specific; requires that all banks are idle. 8. may or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. deep power-down is power savings feature of this mobile sdram device. this command is burst terminate when cke is high and deep power down when cke is low. 10. reads or writes listed in the command (action) column include reads or writes with auto precharge enabled and reads or write s with auto precharge disabled. 11. does not affect the state of the bank and acts as a nop to that bank. table 8: truth table 3 ? current state bank n , command to bank n notes: 1-6; notes appear below table current state cs# ras# cas# we# command (action) notes any h x x x command inhibit (nop/contin ue previous operation) lhhh no operation (nop/continue previous operation) idle l l h h active (select and activate row) lllh auto refresh 7 llll load mode register 7 llhl precharge 11 row activelhlh read (select column and start read burst) 10 lhl l write (select column and start write burst) 10 llhl precharge (deactivate row in bank or banks) 8 read (auto precharge disabled) lhlh read (select column and start new read burst) 10 lhl l write (select column and start write burst) 10 llhl precharge (truncate read burst, start precharge) 8 lhhl burst terminate 9 write (auto precharge disabled) lhlh read (select column and start read burst) 10 lhl l write (select column and start new write burst) 10 llhl precharge (truncate write burst, start precharge) 8 lhhl burst terminate 9
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 28 ?2003 micron technology, inc. all rights reserved. note: 1. this table applies when cke n-1 was high and cke n is high (see truth table 2) and after t xsr has been met (if the previ- ous state was self refresh). 2. this table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the com- mands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given com- mand is allowable). exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no regis- ter accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled, and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto precharge enabled: starts with registration of a write command with auto precharge enabled, and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 4. auto refresh, self refresh and load mode register commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved. table 9: truth table 4 ? current state bank n , command to bank m notes: 1-6; notes appear below and on next page current state cs# ras # cas # we# command (action) notes any h x x x command inhibit (nop/continue previous operation) lhhh no operation (nop/continue previous operation) idle x x x x any command otherwise allowed to bank m row activating, active, or precharging llhh active (select and activate row) lhl h read (select column and start read burst) 7 lhl l write (select column and start write burst) 7 llhl precharge read (auto precharge disabled) llhh active (select and activate row) lhl h read (select column and start new read burst) 7, 10 lhl l write (select column and start write burst) 7, 11 llhl precharge 9 write (auto precharge disabled) llhh active (select and activate row) lhl h read (select column and start read burst) 7, 12 lhl l write (select column and start new write burst) 7, 13 llhl precharge 9 read (with auto precharge) llhh active (select and activate row) lhl h read (select column and start new read burst) 7, 8, 14 lhl l write (select column and start write burst) 7, 8, 15 llhl precharge 9 write (with auto precharge) llhh active (select and activate row) lhl h read (select column and start read burst) 7, 8, 16 lhl l write (select column and start new write burst) 7, 8, 17 llhl precharge 9
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 29 ?2003 micron technology, inc. all rights reserved. 7. reads or writes to bank m listed in the command (action) column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. concurrent auto precharge: bank n will initiate the auto precharge command when its burst has been interrupted by bank m ?s burst. 9. burst in bank n continues as initiated. 10. for a read without auto precharge interrupted by a re ad (with or without auto precharge), the read to bank m will interrupt the read on bank n , cas latency later (figure 10, consecutive read bursts, on page 17). 11. for a read without auto precharge interrupted by a writ e (with or without auto precharge), the write to bank m will interrupt the read on bank n when registered (figure 12, read to writ e, on page 18, and figure 13, read to write with extra clock cycle, on page 18). dqm should be used one clock prior to the write command to prevent bus conten- tion. 12. for a write without auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the write on bank n when registered (figure 20, write to read , on page 21), with the data-out appearing cas latency later. the last valid write to bank n will be data-in registered one clock prior to the read to bank m . 13. for a write without auto precharge interrupted by a wr ite (with or without auto precharge), the write to bank m will interrupt the write on bank n when registered (figure 18, write to write, on page 20). the last valid write to bank n will be data-in registered one clock prior to the read to bank m . 14. for a read with auto precharge interrupted by a re ad (with or without auto precharge), the read to bank m will interrupt the read on bank n , cas latency later (figure 27, read with auto precharge interrupted by a read, on page 24). the precharge to bank n will begin when the read to bank m is registered. 15. for a read with auto precharge interrupted by a writ e (with or without auto precharge), the write to bank m will interrupt the read on bank n when registered (figure 28, read with auto precharge interrupted by a write, on page 24). dqm should be used two clocks prior to the writ e command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered. 16. for a write with auto precharge interrupted by a re ad (with or without auto precharge), the read to bank m will interrupt the write on bank n when registered, with the data-out appearing cas latency later (figure 29, write with auto precharge interrupted by a read, on page 25). the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write bank n will be data-in registered one clock prior to the read to bank m . 17. for a write with auto precharge interrupted by a writ e (with or without auto precharge), the write to bank m will interrupt the write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered (figure 30, write with auto precharge interrupted by a write, on page 25). the last valid write to bank n will be data registered one clock to the write to bank m .
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 30 ?2003 micron technology, inc. all rights reserved. absolute maximum ratings stresses greater than those listed may cause perma- nent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. voltage on v dd /v dd q supply relative to v ss . . . . . . . . . . . . . . . . . . . -0.35v to +2.8v voltage on inputs, nc or i/o pins relative to v ss . . . . . . . . . . . . . . . . . . . -0.35v to +2.8v operating temperature t a (extended) . . . . . . . . . . . . . . . . . . . .-25c to +85c t a (industrial) . . . . . . . . . . . . . . . . . . . .-40c to +85c storage temperature (plastic) . . . . .-55c to +150c table 10: dc electrical characteristics and operating conditions notes: 1, 5, 6; notes appear on page 34; v dd = v dd q = +1.8v 0.1v parameter/condition symbol min max units notes supply voltage v dd 1.7 1.9 v i/o supply voltage v dd q1.71.9 v input high voltage: logic 1; all inputs v ih 0.8 x v dd qv dd +0.3 v 22 input low voltage: logic 0; all inputs v il -0.3 +0.3 v 22 output high voltage: all inputs v oh 0.9 x v dd q? v output low voltage: all inputs v ol ?0.2v input leakage current: any input 0v v in v dd (all other pins not under test = 0v) i i -1.0 1.0 a output leakage current: dq disabled; 0v v out v dd q i oz -1.5 1.5 a table 11: ac electrical characteristics and operating conditions v dd = 1.7v - 1.9v; v dd q = 1.7v - 1.9v parameter/condition symbol min max units notes input high voltage: logic 1; all inputs v ih 1.4 - v input low voltage: logic 0; all inputs v il -+0.4v
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 31 ?2003 micron technology, inc. all rights reserved. table 12: electrical characteristics and recommended ac operating conditions notes: 5, 6, 8, 9, 11; notes appear on page 34 ac characteristics -8 -10 units notes parameter symbol min max min max access time from clk (pos. edge) cl = 3 t ac (3) 67ns27 cl = 2 t ac (2) 88ns address hold time t ah 11ns address setup time t as 2.5 2.5 ns clk high-level width t ch 33ns clk low-level width t cl 33ns clock cycle time cl = 3 t ck (3) 8 100 9.6 100 ns 23 cl = 2 t ck (2) 9.6 100 12 100 ns 23 cke hold time t ckh 11ns cke setup time t cks 1.5 2.5 ns cs#, ras#, cas#, we#, dqm hold time t cmh 11ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 2.5 ns data-in hold time t dh 11ns data-in setup time t ds 2.5 2.5 ns data-out high-impedance time cl = 3 t hz (3) 77ns10 cl = 2 t hz (2) 88ns10 data-out low-impedance time t lz 11ns data-out hold time (load) t oh 2.5 2.5 ns data-out hold time (no load) t oh n 1.8 1.8 ns 28 active to precharge command t ras 48 120,000 50 120,000 ns active to active command period t rc 80 100 ns active to read or write delay t rcd 19 20 ns refresh period (4,096 rows) t ref 64 64 ms auto refresh period t rfc 80 100 ns precharge command period t rp 19 20 ns active bank a to active bank b command t rrd 16 20 ns transition time t t 0.5 1.2 0.3 1.2 ns 7 write recovery time t wr (a) 1 clk +7ns 1 clk +5ns ?24 t wr (m) 15 15 ns 25 exit self refresh to active command t xsr 80 100 ns 20
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 32 ?2003 micron technology, inc. all rights reserved. table 13: ac functional characteristics notes: 5, 6, 7, 8, 9, 11; notes appear on page 34 parameter symbol -8 -10 units notes read/write command to read/write command t ccd 11 t ck 17 cke to clock disable or power-down entry mode t cked 11 t ck 14 cke to clock enable or power-down exit setup mode t ped 11 t ck 14 dqm to input data delay t dqd 00 t ck 17 dqm to data mask during writes t dqm 00 t ck 17 dqm to data high-impedance during reads t dqz 22 t ck 17 write command to input data delay t dwd 00 t ck 17 data-in to active command t dal 55 t ck 15, 21 data-in to precharge command t dpl 22 t ck 16, 21 last data-in to burst stop command t bdl 11 t ck 17 last data-in to new read/write command t cdl 11 t ck 17 last data-in to precharge command t rdl 22 t ck 16, 21 load mode register command to active or refresh command t mrd 22 t ck 26 data-out to high-impedance from precharge command cl = 3 t roh(3) 33 t ck 17 cl = 2 t roh(2) 22 t ck 17 ta bl e 1 4 : i dd specifications and conditions notes: 1, 5, 6, 11, 13, 32; notes appear on page 34; v dd = v dd q = +1.8v 0.1v max parameter/condition symbol -8 -10 units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd1 50 50 ma 3, 18, 19 standby current: power-down mode; all banks idle; cke = low i dd 2 150 150 a 32 standby current: active mode; cke = high; cs# = high; all banks active after t rcd met; no accesses in progress i dd3 35 30 ma 3, 12, 19 operating current: burst mode; continuous burst; read or write; all banks active i dd4 50 50 ma 3, 18, 19 auto refresh current cke = high; cs# = high t rc = t rfc (min) i dd5 60 50 ma 3, 12, 18, 19, 33 t rfc = 15.625s i dd6 22ma deep power down i zz 10 10 a 34
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 33 ?2003 micron technology, inc. all rights reserved. ta bl e 1 5 : i dd 7 - self refresh current options notes: 4; notes appear on page 34; v dd = v dd q = +1.8v 0.1v temperature compensated self refresh parameter/condition max temperature -8 & -10 units notes self refresh current: cke < 0.2v ? 4 banks open 85oc 160 a 4 70oc 130 a 4 45oc 110 a 4 15oc 100 a 4 self refresh current: cke < 0.2v ? 2 banks open 85oc 130 a 4 70oc 100 a 4 45oc 90 a 4 15oc 80 a 4 self refresh current: cke < 0.2v ? 1 bank open 85oc 110 a 4 70oc 80 a 4 45oc 70 a 4 15oc 65 a 4 self refresh current: cke < 0.2v ? 1/2 bank open 85oc 105 a 4 70oc 75 a 4 45oc 65 a 4 15oc 65 a 4 self refresh current: cke < 0.2v ? 1/4 bank open 85oc 100 a 4 70oc 75 a 4 45oc 65 a 4 15oc 65 a 4 table 16: capacitance note: 2; notes appear following on page 34 parameter symbol min max units notes input capacitance: clk c i 1 1.5 4.0 pf 29 input capacitance: all other input-only pins c i2 1.5 4.0 pf 30 input/output capacitance: dq c io 3.0 6.0 pf 31
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 34 ?2003 micron technology, inc. all rights reserved. notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd , v dd q = +1.8v; t a = 25c; pin under test biased at 1.4v. f = 1 mhz. 3. i dd is dependent on output loading and cycle rates. specified values are obtained with mini- mum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-25c t a +85c for standard parts; -40c t a +85c for it parts) is ensured. 6. an initial pause of 100s is required after power- up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v dd q must be powered up simultaneously. v ss and v ss q must be at same potential.) the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specifi- cation, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a mono- tonic manner. 9. outputs measured for 1.8v at 0.9v with equivalent load: 10. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i dd tests have v il and v ih , with timing referenced to v ih /2 = crossover point. if the input transition time is longer than t t (max), then the timing is referenced at v il (max) and v ih (min) and no longer at the v ih /2 crossover point. 12. other input signals are allowed to transition no more than once every two clocks and are other- wise at valid v ih or v il levels. 13. i dd specifications are tested after the device is properly initialized. 14. timing actually specified by t cks; clock(s) speci- fied as a reference only at minimum cycle rate. 15. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 16. timing actually specified by t wr. 17. required clocks are specified by jedec function- ality and are not dependent on any timing param- eter. 18. the i dd current will increase or decrease propor- tionally according to the amount of frequency alteration for the test condition. 19. address transitions average one transition every two clocks. 20. clk must be toggled a minimum of two times during this period. 21. based on t ck = 8ns for -8 and t ck = 9.6ns for -10. 22. v ih overshoot: v ih (max) = v dd q + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il under- shoot: v il (min) = -2v for a pulse width 3ns. 23. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (read, write, includ- ing t wr, and precharge commands). cke may be used to reduce the data rate. 24. auto precharge mode only. the precharge timing budget ( t rp) begins at 7ns for -8 after the first clock delay, after the last write is executed. may not exceed limit set for precharge mode. 25. precharge mode only. 26. jedec and pc100 specify three clocks. 27. t ac for -8 at cl = 3 with no load is 7ns and is guar- anteed by design. 28. parameter guaranteed by design. 29. pc100 specifies a maximum of 4pf. 30. pc100 specifies a maximum of 5pf. 31. pc100 specifies a maximum of 6.5pf. 32. for -8, cl = 2, t ck = 9.6ns. for -10, cl = 3 and t ck = 9.6ns. 33. cke is high during refresh command period t rfc (min) else cke is low. the i dd 6 limit is actually a nominal value and does not result in a fail value. 34. deep power down current is a nominal value at 25c. the parameter is not tested. q 30pf
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 35 ?2003 micron technology, inc. all rights reserved. figure 31: initialize and load mode register 1 note: 1. pre = precharge command, lmr = load mode register command, ar = auto refresh command, act = active command, ra = row address, ba = bank address 2. optional refresh command. 3. device timing is -10 with 104 mhz clock. symbol 1 note: 1. cas latency indicated in parentheses. -8 -10 units symbol -8 -10 units min max min max min max min max t ah 11ns t ckh 11ns t as 2.5 2.5 ns t cks 2.5 2.5 ns t ch 33ns t cmh 11ns t cl 33ns t cms 2.5 2.5 ns t ck (3) 8 100 9.6 100 ns t mrd 22 t ck t ck (2) 9.6 100 12 100 ns t rfc 80 100 ns t rp 19 20 ns cke ba0, ba1 load extended mode register load mode register t cks power-up: v dd and clk stable t = 100s t ckh ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dqml, dqmu ( ) ( ) ( ) ( ) dq high-z a0-a9, a11 ra a10 ra all banks clk t ck command 3 ar nop lmr ar lmr pre 2 act t cms t cmh t as t ah ba0 = l, ba1 = l ( ) ( ) ( ) ( ) code code t as t ah code code ( ) ( ) ( ) ( ) pre all banks t as t ah ( ) ( ) ( ) ( ) t0 t1 t3 t5 t7 t9 t19 t29 don?t care ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rp t mrd t mrd t rp t rfc t rfc ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ra ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ba0 = l, ba1 = h ba0 = l, ba1 = h t as t ah ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 36 ?2003 micron technology, inc. all rights reserved. figure 32: power-down mode 1 note: 1. violating refresh requirements during power-down may result in a loss of data. t ch t cl t ck two clock cycles cke clk dq all banks idle, enter power-down mode precharge all active banks input buffers gated off while in power-down mode exit power-down mode ( ) ( ) ( ) ( ) don?t care t cks t cks command t cmh t cms precharge nop nop active nop ( ) ( ) ( ) ( ) all banks idle ba0, ba1 bank bank(s) ( ) ( ) ( ) ( ) high-z t ah t as t ckh t cks dqml, dqmu ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) a0-a9, a11 row ( ) ( ) ( ) ( ) all banks single bank a10 row ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 tn + 2 symbol 1 -8 -10 units symbol -8 -10 units min max min max min max min max t ah 11ns t ckh 11ns t as 2.5 2.5 ns t cks 2.5 2.5 ns t ch 33ns t cmh 11ns t cl 33ns t cms 2.5 2.5 ns t ck (3) 8 100 9.6 100 ns t mrd 22 t ck t ck (2) 9.6 100 12 100 ns t rfc 80 100 ns t rp 19 20 ns note: 1. cas latency indicated in parentheses.
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 37 ?2003 micron technology, inc. all rights reserved. figure 33: clock suspend mode note: 1. for this example, the burst length = 2, the cas latency = 3, and auto precharge is disabled. 2. a9 and a11 = ?don?t care.? t ch t cl t ck t ac t lz dqmu, dqml clk a0-a9, a11 dq ba0, ba1 a10 t oh d out m t ah t as t ah t as t ah t as bank t dh d out e t ac t hz d out m + 1 command t cmh t cms nop nop nop nop nop read write undefined cke t cks t ckh bank column m t ds d out e + 1 nop t ckh t cks t cmh t cms 2 column e 2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 don?t care symbol 1 -8 -10 units symbol -8 -10 units min max min max min max min max t ac (3) 77ns t cks 2.5 2.5 ns t ac (2) 88ns t cmh 11 ns t ah 11 ns t cms 2.5 2.5 ns t as 2.5 2.5 ns t dh 11 ns t ch 33 ns t ds 2.5 2.5 ns t cl 33 ns t hz (3) 77ns t ck (3) 8 100 9.6 100 ns t hz (2) 78ns t ck (2) 9.6 100 12 100 ns t lz 11 ns t ckh 11 ns t oh 2.5 2.5 ns note: 1. cas latency indicated in parentheses.
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 38 ?2003 micron technology, inc. all rights reserved. figure 34: auto refresh mode note: 1. each auto refresh command performs a refresh cycle. back-to-back commands are not required. t ch t cl t ck cke clk dq t rfc 1 ( ) ( ) ( ) ( ) ( ) ( ) t rp ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) command t cmh t cms nop nop ( ) ( ) ( ) ( ) bank active auto refresh ( ) ( ) ( ) ( ) nop nop precharge precharge all active banks auto refresh t rfc 1 high-z ba0, ba1 bank(s) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t ah t as t ckh t cks ( ) ( ) nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dqmu, dqml a0-a9, a11 row ( ) ( ) ( ) ( ) all banks single bank a10 row ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 to + 1 don?t care symbol 1 -8 -10 units symbol -8 -10 units min max min max min max min max t ah 11 ns t ckh 11ns t as 2.5 2.5 ns t cks 2.5 2.5 ns t ch 33 ns t cmh 11ns t cl 33 ns t cms 2.5 2.5 ns t ck (3) 8 100 9.6 100 ns t mrd 22 t ck t ck (2) 9.6 100 12 100 ns t rfc 80 100 ns t rp 19 20 ns note: 1. cas latency indicated in parentheses.
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 39 ?2003 micron technology, inc. all rights reserved. figure 35: self refresh mode note: 1. each auto refresh command performs a refresh cycle. back-to-back commands are not required. t ch t cl t ck t rp cke clk dq enter self refresh mode precharge all active banks t xsr clk stable prior to exiting self refresh mode exit self refresh mode (restart refresh time base) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) command t cmh t cms auto refresh precharge nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ba0, ba1 bank(s) high-z t cks ah as auto refresh > t ras ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t ckh t cks dqmu, dqml ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t t a0-a9, a11 ( ) ( ) ( ) ( ) all banks single bank a10 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 to + 1 to + 2 ( ) ( ) ( ) ( ) don?t care symbol 1 -8 -10 units symbol -8 -10 units min max min max min max min max t ah 11ns t ckh 11 ns t as 2.5 2.5 ns t cks 2.5 2.5 ns t ch 33ns t cmh 11 ns t cl 33ns t cms 2.5 2.5 ns t ck (3) 8 100 9.6 100 ns t ras 48 120,000 50 120,000 ns t ck (2) 9.6 100 12 100 ns t rp 19 20 ns t xsr 80 100 ns note: 1. cas latency indicated in parentheses.
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 40 ?2003 micron technology, inc. all rights reserved. figure 36: read ? without auto precharge1 note: 1. for this example, the burst length = 4, the cas latency = 2, and the read burst is followed by a ?manual? precharge. 2. a9 and a11 = ?don?t care.? symbol 1 note: 1. cas latency indicated in parentheses. -8 -10 units symbol -8 -10 units min max min max min max min max t ac (3) 77ns t cmh 11ns t ac (2) 88ns t cms 2.5 2.5 ns t ah 11ns t hz (3) 77ns t as 2.5 2.5 ns t hz (2) 88ns t ch 33ns t lz 11ns t cl 33ns t oh 2.5 2.5 ns t ck (3) 8 100 9.6 100 ns t ras 48 120,000 50 120,000 ns t ck (2) 9.6 100 12 100 ns t rc 80 100 ns t ckh 11ns t rcd 19 20 ns t cks 2.5 2.5 ns t rp 19 20 ns all banks t ch t cl t ck t ac t lz t rp t ras t rcd cas latency t rc t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank(s) bank row row bank t hz t oh d out m +3 t ac t oh t ac t oh t ac d out m +2 d out m +1 t cmh t cms precharge nop nop nop active nop read nop active disable auto precharge single banks column m 2 t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8 dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 command don?t care undefined
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 41 ?2003 micron technology, inc. all rights reserved. figure 37: read ? with auto precharge 1 note: 1. for this example, the burst length = 4, the cas latency = 2. 2. a9 and a11 = ?don?t care.? symbol 1 note: 1. cas latency indicated in parentheses. -8 -10 units symbol -8 -10 units min max min max min max min max t ac (3) 77ns t cmh 11 ns t ac (2) 88ns t cms 2.5 2.5 ns t ah 11ns t hz (3) 77ns t as 2.5 2.5 ns t hz (2) 88ns t ch 33ns t lz 11 ns t cl 33ns t oh 33 ns t ck (3) 8 100 9.6 100 ns t ras 48 120,000 50 120,000 ns t ck (2) 9.6 100 12 100 ns t rc 80 100 ns t ckh 11ns t rcd 19 20 ns t cks 1.5 2.5 ns t rp 19 20 ns enable auto precharge t ch t cl t ck t ac t lz t rp t ras t rcd cas latency t rc dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank row row bank t hz t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms nop nop nop active nop read nop active nop t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 undefined don?t care
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 42 ?2003 micron technology, inc. all rights reserved. figure 38: single read ? without auto precharge 1 note: 1. for this example, the burst length = 4, the cas latency = 2, and the read burst is followed by a ?manual? precharge. 2. a9 and a11 = ?don?t care.? 3. precharge command not allowed or t ras would be violated. symbol 1 note: 1. cas latency indicated in parentheses. -8 -10 units symbol -8 -10 units min max min max min max min max t ac (3) 77ns t cmh 11ns t ac (2) 88ns t cms 2.5 2.5 ns t ah 11 ns t hz (3) 77ns t as 2.5 2.5 ns t hz (2) 88ns t ch 33 ns t lz 11ns t cl 33 ns t oh 33ns t ck (3) 8 100 9.6 100 ns t ras 48 120,000 50 120,000 ns t ck (2) 9.6 100 12 100 ns t rc 80 66 ns t ckh 11 ns t rcd 19 20 ns t cks 2.5 2.5 ns t rp 19 20 ns all banks t ch t cl t ck t ac t lz t rp t ras t rcd cas latency t rc t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank(s) bank row row bank t hz t cmh t cms nop nop nop precharge active nop read active nop disable auto precharge single banks column m 2 t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8 dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 command 3 3 undefined don?t care
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 43 ?2003 micron technology, inc. all rights reserved. figure 39: single read ? with auto precharge 1 note: 1. for this example, the burst length = 4, the cas latency = 2, and the read burst is followed by a ?manual? precharge. 2. a9 and a11 = ?don?t care.? 3. precharge command not allowed or t ras would be violated. symbol 1 note: 1. cas latency indicated in parentheses. -8 -10 units symbol -8 -10 units min max min max min max min max t ac (3) 77ns t cmh 11ns t ac (2) 88ns t cms 2.5 2.5 ns t ah 11 ns t hz (3) 77ns t as 2.5 2.5 ns t hz (2) 88ns t ch 33 ns t lz 11ns t cl 33 ns t oh 33ns t ck (3) 8 100 9.6 100 ns t ras 48 120,000 50 120,000 ns t ck (2) 9.6 100 12 100 ns t rc 80 66 ns t ckh 11 ns t rcd 19 20 ns t cks 2.5 2.5 ns t rp 19 20 ns enable auto precharge t ch t cl t ck t rp t ras t rcd cas latency t rc dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as t ah t as t ah t as row row bank bank row row bank t hz t oh d out m t ac command t cmh t cms nop 3 read active nop nop 3 active nop t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 nop nop undefined don?t care
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 44 ?2003 micron technology, inc. all rights reserved. figure 40: alternating bank read accesses 1 note: 1. for this example, the burst length = 4, the cas latency = 2. 2. a9 and a11 = ?don?t care.? symbol 1 note: 1. cas latency indicated in parentheses. -8 -10 units symbol -8 -10 units min max min max min max min max t ac (3) 77ns t cmh 11 ns t ac (2) 88ns t cms 2.5 2.5 ns t ah 11ns t hz (3) 77ns t as 2.5 2.5 ns t hz (2) 88ns t ch 33ns t lz 11 ns t cl 33ns t oh 33 ns t ck (3) 8 100 9.6 100 ns t ras 48 120,000 50 120,000 ns t ck (2) 9.6 100 12 100 ns t rc 80 66 ns t ckh 11ns t rcd 19 20 ns t cks 2.5 2.5 ns t rp 19 20 ns t rrd 16 20 ns enable auto precharge t ch t cl t ck t ac t lz dqmu, dqml clk a0-a9, a11 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row row row t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms nop nop active nop read nop active t oh d out b t ac t ac read enable auto precharge row active row bank 0 bank 0 bank 3 bank 3 bank 0 cke t ckh t cks column m 2 column b 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t rp - bank 0 t ras - bank 0 t rcd - bank 0 t rcd - bank 0 cas latency - bank 0 t rcd - bank 3 cas latency - bank 3 t t rc - bank 0 rrd undefined don?t care
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 45 ?2003 micron technology, inc. all rights reserved. figure 41: read ? full-page burst 1 note: 1. for this example, the cas latency = 2. 2. a9 and a11 = ?don?t care.? 3. page left open; no t rp. symbol 1 note: 1. cas latency indicated in parentheses. -8 -10 units symbol -8 -10 units min max min max min max min max t ac (3) 77ns t cmh 11 ns t ac (2) 88ns t cms 2.5 2.5 ns t ah 11ns t hz (3) 77ns t as 2.5 2.5 ns t hz (2) 88ns t ch 33ns t lz 11 ns t cl 33ns t oh 33 ns t ck (3) 8 100 9.6 100 ns t ras 48 120,000 50 120,000 ns t ck (2) 9.6 100 12 100 ns t rc 80 66 ns t ckh 11ns t rcd 19 20 ns t cks 2.5 2.5 ns t rp 19 20 ns t rrd 16 20 ns t ch t cl t ck t ac t lz t rcd cas latency dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ac t oh d out m +1 row row t hz t ac t oh d out m +1 t ac t oh d out m +2 t ac t oh d out m -1 t ac t oh d out m full-page burst does not self-terminate. can use burst terminate command. ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed 256 (x16) locations within same row don?t care undefined command t cmh t cms nop nop nop active nop read nop burst term nop nop ( ) ( ) ( ) ( ) nop ( ) ( ) ( ) ( ) t ah t as bank ( ) ( ) ( ) ( ) bank t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) column m 2 3 t0 t1 t2 t4 t3 t5 t6 tn + 1 tn + 2 tn + 3 tn + 4
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 46 ?2003 micron technology, inc. all rights reserved. figure 42: read ? dqm operation 1 note: 1. for this example, the cas latency = 2. 2. a9 and a11 = ?don?t care.? symbol 1 note: 1. cas latency indicated in parentheses. -8 -10 units symbol -8 -10 units min max min max min max min max t ac (3) 77ns t cmh 11ns t ac (2) 88ns t cms 2.5 2.5 ns t ah 11ns t hz (3) 77ns t as 2.5 2.5 ns t hz (2) 88ns t ch 33ns t lz 11ns t cl 33ns t oh 2.5 2.5 ns t ck (3) 8 100 9.6 100 ns t ras 48 120,000 50 120,000 ns t ck (2) 9.6 100 12 100 ns t rc 80 66 ns t ckh 11ns t rcd 19 20 ns t cks 2.5 2.5 ns t rp 19 20 ns t rrd 16 20 ns t ch t cl t ck t rcd cas latency dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 t cms row bank row bank t ac lz d out m t oh d out m + 3 d out m + 2 t t hz lz t t cmh command nop nop nop active nop read nop nop nop t hz t ac t oh t ac t oh t ah t as t cms t cmh t ah t as t ah t as t ckh t cks enable auto precharge disable auto precharge column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 undefined don?t care
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 47 ?2003 micron technology, inc. all rights reserved. figure 43: write ? without auto precharge 1 note: 1. for this example, the burst length = 4, and the write burst is followed by a ?manual? precharge. 2. 15ns is required between and the precharge command, regardless of frequency. 3. a9 and a11 = ?don?t care.? symbol 1 note: 1. cas latency indicated in parentheses. -8 -10 units symbol -8 -10 units min max min max min max min max t ac (3) 77ns t cmh 11ns t ac (2) 88ns t cms 2.5 2.5 ns t ah 11 ns t dh 11ns t as 2.5 2.5 ns t ds 2.5 2.5 ns t ch 33 ns t ras 48 120,000 50 120,000 ns t cl 33 ns t rc 80 100 ns t ck (3) 8 100 9.6 100 ns t rcd 19 20 ns t ck (2) 9.6 100 12 100 ns t rp 19 20 ns t ckh 11 ns t wr (a) 1 clk +7ns 1 clk +5ns ? t cks 2.5 2.5 ns t wr (m) 15 15 ns disable auto precharge all banks t ch t cl t ck t rp t ras t rcd t rc dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as row row bank bank bank row row bank t wr d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop nop active nop write nop precharge active t ah t as t ah t as t dh t ds t dh t ds t dh t ds single bank t ckh t cks column m 3 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 nop don?t care
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 48 ?2003 micron technology, inc. all rights reserved. figure 44: write ? with auto precharge 1 note: 1. for this example, the burst length = 4. 2. a9 and a11 = ?don?t care.? symbol 1 note: 1. cas latency indicated in parentheses. -8 -10 units symbol -8 -10 units min max min max min max min max t ac (3) 77ns t cmh 11ns t ac (2) 88ns t cms 2.5 2.5 ns t ah 11 ns t dh 11ns t as 2.5 2.5 ns t ds 2.5 2.5 ns t ch 33 ns t ras 48 120,000 50 120,000 ns t cl 33 ns t rc 80 100 ns t ck (3) 8 100 9.6 100 ns t rcd 19 20 ns t ck (2) 9.6 100 12 100 ns t rp 19 20 ns t ckh 11 ns t wr (a) 1 clk +7ns 1 clk +5ns ? t cks 2.5 2.5 ns t wr (m) 15 15 ns enable auto precharge t ch t cl t ck t rp t ras t rcd t rc dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as row row bank bank row row bank t wr d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop nop active nop write nop active t ah t as t ah t as t dh t ds t dh t ds t dh t ds t ckh t cks nop nop column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 don?t care
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 49 ?2003 micron technology, inc. all rights reserved. figure 45: single write ? without auto precharge 1 note: 1. for this example, the burst length = 1, and the write burst is followed by a ?manual? precharge. 2. 15ns is required between and the precharge command, regardless of frequency. 3. a9 and a11 = ?don?t care.? 4. precharge command not allowed else t ras would be violated. symbol 1 note: 1. cas latency indicated in parentheses. -8 -10 units symbol -8 -10 units min max min max min max min max t ac (3) 77ns t cmh 11ns t ac (2) 88ns t cms 2.5 2.5 ns t ah 11 ns t dh 11ns t as 2.5 2.5 ns t ds 2.5 2.5 ns t ch 33 ns t ras 48 120,000 50 120,000 ns t cl 33 ns t rc 80 100 ns t ck (3) 8 100 9.6 100 ns t rcd 19 20 ns t ck (2) 9.6 100 12 100 ns t rp 19 20 ns t ckh 11 ns t wr (a) 1 clk +7ns 1 clk +5ns ? t cks 2.5 2.5 ns t wr (m) 15 15 ns disable auto precharge all banks t ch t cl t ck t rp t ras t rcd t rc dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as row bank bank bank row row bank t wr d in m t dh t ds command t cmh t cms nop 4 nop 4 precharge active nop write active nop nop t ah t as t ah t as single bank t ckh t cks column m 3 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 don?t care
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 50 ?2003 micron technology, inc. all rights reserved. figure 46: single write ? with auto precharge 1 note: 1. for this example, the burst length = 1, and the write burst is followed by a ?manual? precharge. 2. 15ns is required between and the precharge command, regardless of frequency. 3. a9 and a11 = ?don?t care.? 4. write command not allowed else t ras would be violated. symbol 1 note: 1. cas latency indicated in parentheses. -8 -10 units symbol -8 -10 units min max min max min max min max t ac (3) 77ns t cmh 11ns t ac (2) 88ns t cms 2.5 2.5 ns t ah 11 ns t dh 11ns t as 2.5 2.5 ns t ds 2.5 2.5 ns t ch 33 ns t ras 48 120,000 50 120,000 ns t cl 33 ns t rc 80 100 ns t ck (3) 8 100 9.6 100 ns t rcd 19 20 ns t ck (2) 9.6 100 12 100 ns t rp 19 20 ns t ckh 11 ns t wr (a) 1 clk +7ns 1 clk +5ns ? t cks 2.5 2.5 ns t wr (m) 15 15 ns enable auto precharge t ch t cl t ck t rp t ras t rcd t rc dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as row row bank bank row row bank t wr d in m command t cmh t cms nop 3 nop 3 nop active nop 3 write nop active t ah t as t ah t as t dh t ds t ckh t cks nop nop column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 don?t care
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 51 ?2003 micron technology, inc. all rights reserved. figure 47: alternating bank write accesses 1 note: 1. for this example, the burst length = 4. 2. a9 and a11 = ?don?t care.? symbol 1 note: 1. cas latency indicated in parentheses. -8 -10 units symbol -8 -10 units min max min max min max min max t ac (3) 77ns t cmh 11ns t ac (2) 88ns t cms 2.5 2.5 ns t ah 11ns t dh 11ns t as 2.5 2.5 ns t ds 2.5 2.5 ns t ch 33ns t ras 48 120,000 50 120,000 ns t cl 33ns t rc 80 100 ns t ck (3) 8 100 9.6 100 ns t rcd 19 20 ns t ck (2) 9.6 100 12 100 ns t rp 19 20 ns t ckh 11ns t wr (a) 1 clk +7ns 1 clk +5ns ? t cks 2.5 2.5 ns t wr (m) 15 15 ns don?t care t ch t cl t ck clk dq d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop active nop write nop nop active t dh t ds t dh t ds t dh t ds active write d in b t dh t ds d in b + 1 d in b + 3 t dh t ds t dh t ds enable auto precharge dqmu, dqml a0-a9, a11 ba0, ba1 a10 t cmh t cms t ah t as t ah t as t ah t as row row row row enable auto precharge row row bank 0 bank 0 bank 1 bank 0 bank 1 cke t ckh t cks d in b + 2 t dh t ds column b 2 column m 2 t rp - bank 0 t ras - bank 0 t rcd - bank 0 t t rcd - bank 0 t wr - bank 0 wr - bank 1 t rcd - bank 1 t t rc - bank 0 rrd t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 52 ?2003 micron technology, inc. all rights reserved. figure 48: write ? full-page burst 1 note: 1. a9 and a11 = ?don?t care.? 2. t wr must be satisfied prior to precharge command. 3. page left open; no t rp. symbol 1 note: 1. cas latency indicated in parentheses. -8 -10 units symbol -8e -10 units min max min max min max min max t ac (3) 77ns t cmh 11ns t ac (2) 88ns t cms 2.5 2.5 ns t ah 11ns t dh 11ns t as 2.5 2.5 ns t ds 2.5 2.5 ns t ch 33ns t ras 48 120,000 50 120,000 ns t cl 33ns t rc 80 100 ns t ck (3) 8 100 9.6 100 ns t rcd 19 20 ns t ck (2) 9.6 100 12 100 ns t rp 19 20 ns t ckh 11ns t wr (a) 1 clk +7ns 1 clk +5ns ? t cks 2.5 2.5 ns t wr (m) 15 15 ns t ch t cl t ck t rcd dqmu, dqml cke clk a0-a9, a11 ba0, ba1 a10 t cms t ah t as t ah t as row row full-page burst does not self-terminate. can use burst terminate command to stop. 2, 3 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed don?t care command t cmh t cms nop nop nop active nop write burst term nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 t dh t ds t dh t ds t dh t ds d in m - 1 t dh t ds t ah t as bank ( ) ( ) ( ) ( ) bank t cmh t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 256 (x16) locations within same row column m 1 t0 t1 t2 t3 t4 t5 tn + 1 tn + 2 tn + 3
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 53 ?2003 micron technology, inc. all rights reserved. figure 49: write ? dqm operation 1 note: 1. for this example, the burst length = 4. 2. a9 and a11 = ?don?t care.? symbol 1 note: 1. cas latency indicated in parentheses. -8 -10 units symbol -8 -10 units min max min max min max min max t ac (3) 77ns t cmh 11ns t ac (2) 88ns t cms 2.5 2.5 ns t ah 11ns t dh 11ns t as 2.5 2.5 ns t ds 2.5 2.5 ns t ch 33ns t ras 48 120,000 50 120,000 ns t cl 33ns t rc 80 100 ns t ck (3) 8 100 9.6 100 ns t rcd 19 20 ns t ck (2) 9.6 100 12 100 ns t rp 19 20 ns t ckh 11ns t wr (a) 1 clk +7ns 1 clk +5ns ? t cks 2.5 2.5 ns t wr (m) 15 15 ns don?t care t ch t cl t ck t rcd dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 t cms t ah t as row bank row bank enable auto precharge d in m + 3 t dh t ds d in m d in m + 2 t cmh command nop nop nop active nop write nop nop t cms t cmh t dh t ds t dh t ds t ah t as t ah t as disable auto precharge t ckh t cks column m 2 t0 t1 t2 t3 t4 t5 t6 t7
64mb: x16 mobile sdram pdf: 09005aef80a63953, source: 09005aef808a7edc micron technology, inc., reserves the right to change products or specifications without notice. y25l_64mb_2.fm - rev. e 11/04 en 54 ?2003 micron technology, inc. all rights reserved. ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.m icron.com, customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. figure 50: 54-ball fbga (8mm x 8mm) note: 1. all dimensions are in millimeters. data sheet designation production : this data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. ball a1 id 0.65 0.05 seating plane 0.10 c c 1.00 max ball a9 0.80 typ 0.80 typ 3.20 0.05 6.40 8.00 0.10 4.00 0.05 solder ball diameter refers to post reflow condition. the pre-reflow diameter is 0.42. 54x ?0.45 0.05 solder ball material: 62% sn, 36% pb, 2% ag solder mask defined ball pads: ?0.40 mold compound: epoxy novolac substrate material: plastic laminate 6.40 3.20 0.05 4.00 0.05 8.00 0.10 c l c l ball a1 id ball a1

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